Analog circuits typically display sensitivity to excessive voltage levels. Transients, such as electrostatic discharges (ESD) can therefore cause the voltage handling capabilities of the analog circuit to be exceeded, resulting in damage to the analog circuit. In order to protect circuits during ESD events, clamps have been devised to shunt current to ground during excessive voltage peaks.
Where multiple ports have to be protected, for instance where multiple pins of a semiconductor device have to be protected, one of two approaches is typically adopted. In the local clamp approach, as shown in FIG. 1, a separate ESD structure, each with an anode and a cathode, is used to protect each port. In the rail based approach two diodes are used to connect each pin between a power rail (power supply bus, Vdd, or ESD+rail) and a ground rail or Vss or ESD-rail, and the two buses or rails are clamped by an ESD triggering clamp.
It will be appreciated that both solutions are highly space intensive. In the local clamp approach for N ports, N additional structures have to be included. In the rail approach for N ports, 2N+1 additional structures have to be included (2N diodes and 1 triggering structure).
What is needed is an ESD solution that requires less space on the chip. The present invention provides such a solution.